`timescale 100ns / 100ps

                       
module tb_sync_gen
    (   output logic                    clk
        );
//*********************** КОНСТАНТЫ ****************************************************************
    localparam ch_num_lp    = 8;
    localparam wl_p         = $clog2(ch_num_lp);
//*********************** СОЗДАНИЕ И ОПИСАНИЕ ПЕРЕМЕННЫХ *******************************************
    logic                   reset_n;
    
    logic                   start;

    logic [31:0]            data;
    logic [31:0]            addr;

    logic vclamp, vsample, vhsync, vhdata, vlsync, vldata, vrsync, vrdata;
    
    integer                 tmp;
    logic [31:0]            mem [0:16*ch_num_lp - 1];
//********************** БЛОК НЕПРЕРЫВНЫХ НАЗНАЧЕНИЙ ASSIGN ****************************************
   
    assign data     = mem[addr[wl_p+3:0]];
//********************** ОПИСАНИЕ ПОДКЛЮЧАЕМЫХ БЛОКОВ ***********************************************
    mod_sync_gen
        // #(  .ch_num (ch_num_lp)
        // )
    mod_sync_gen_inst1
        (   .clk        (clk),
            .reset_n    (reset_n),

            .start      (start),
                    
            .vldata_o   (vldata),
            .vrdata_o   (vrdata),
            .vhdata_o   (vhdata),
            .vlsync_o   (vlsync),
            .vrsync_o   (vrsync),
            .vhsync_o   (vhsync),
            .vsample_o  (vsample),
            .vclamp_o   (vclamp),
                    
                    
            .data_param (data),
            .addr_param (addr)
        );

  
// ********************* БЛОКИ ИНИЦИАЛИЗАЦИИ *******************************************************
    initial begin
        reset_n = 0;
    #25 reset_n = 1;
    end
    
    initial begin        // CLK
        clk = 0;
        forever #5ns clk = ~clk;
    end
    
    initial begin        // CLK

        // repeat (50) begin
            start = 0;
            #100;
            start = 1;
            #50;
            start = 0;
        // end;
    end    
    
    initial begin
        for (int i = 0; i <= 15; i++) begin
            mem[i] = i;
        end
       
        tmp = 0;                        // Vrdata
            mem[tmp + 0] = 100;         // f_delay
            mem[tmp + 1] = 300;         // phase
            mem[tmp + 2] = 1000;       // period
            mem[tmp + 3] = 1;          // up
            mem[tmp + 4] = 1;           // num
            mem[tmp + 5] = 0;           // sync_imp

            mem[tmp + 6] = 500;        // f_delay_group
            mem[tmp + 7] = 0;        // phase_group
            mem[tmp + 8] = 5000;     // period_group            

        tmp = 1 * 16;                   // Vrsync
            mem[tmp + 0] = 100;         // f_delay
            mem[tmp + 1] = 300;         // phase
            mem[tmp + 2] = 1000;       // period
            mem[tmp + 3] = 50;          // up
            mem[tmp + 4] = 1;           // num
            mem[tmp + 5] = 0;           // sync_imp

            mem[tmp + 6] = 500;        // f_delay_group
            mem[tmp + 7] = 0;        // phase_group
            mem[tmp + 8] = 5000;     // period_group     
     
        tmp = 2 * 16;       // Vldata
            mem[tmp + 0] = 1000_0;        // f_delay
            mem[tmp + 1] = 0_0;        // phase
            mem[tmp + 2] = 83300_0;    // period
            mem[tmp + 3] = 10_0;       // up
            mem[tmp + 4] = 1;           // num
            mem[tmp + 5] = 0;           // sync_imp

            mem[tmp + 6] = 0_0;        // f_delay_group
            mem[tmp + 7] = 0_0;        // phase_group
            mem[tmp + 8] = 83300_0;     // period_group    
/*
        tmp = 3 * 16;       // Vlsync
            mem[tmp + 0] = _0;       // f_delay
            mem[tmp + 1] = 25;      // phase
            mem[tmp + 2] = 3300_0;    // period
            mem[tmp + 3] = 5_0;      // up
            mem[tmp + 4] = 241;     // num
            mem[tmp + 5] = 3;       // sync_imp
            
            mem[tmp + 6] = _0;       // f_delay_group
            mem[tmp + 7] = _0;       // phase_group
            mem[tmp + 8] = 1000_0;   // period_group  
            
        tmp = 4 * 16;       // Vhdata
            mem[tmp + 0] = 60_0;     // f_delay
            mem[tmp + 1] = 10_0;     // phase
            mem[tmp + 2] = 3300_0;   // period
            mem[tmp + 3] = 10_0;     // up
            mem[tmp + 4] = 241;     // num
            mem[tmp + 5] = _0;       // sync_imp
            
            mem[tmp + 6] = _0;       // f_delay_group
            mem[tmp + 7] = _0;       // phase_group
            mem[tmp + 8] = 1000_0;   // period_group  
            
        tmp = 5 * 16;       // Vhsync
            mem[tmp + 0] = _0;     // f_delay
            mem[tmp + 1] = 25;      // phase
            mem[tmp + 2] = 10_0;     // period
            mem[tmp + 3] = 5_0;      // up
            mem[tmp + 4] = 32_0;     // num
            mem[tmp + 5] = 5;       // sync_imp
            
            mem[tmp + 6] = _0;       // f_delay_group
            mem[tmp + 7] = _0;       // phase_group
            mem[tmp + 8] = 1000_0;   // period_group  
            
        tmp = 6 * 16;       // Vsample
            mem[tmp + 0] = 60_0;     // f_delay
            mem[tmp + 1] = 11_0;     // phase
            mem[tmp + 2] = 3300_0;   // period
            mem[tmp + 3] = 5_0;    // up
            mem[tmp + 4] = 241;    // num
            mem[tmp + 5] = _0;       // sync_imp
            
            mem[tmp + 6] = _0;       // f_delay_group
            mem[tmp + 7] = _0;       // phase_group
            mem[tmp + 8] = 1000_0;   // period_group  
        
        tmp = 7 * 16;            // Vclamp
            mem[tmp + 0] = 60_0;     // f_delay
            mem[tmp + 1] = 25;      // phase
            mem[tmp + 2] = 10_0;     // period
            mem[tmp + 3] = 5_0;      // up
            mem[tmp + 4] = 32_0;     // num
            mem[tmp + 5] = _0;       // sync_imp
            
            mem[tmp + 6] = _0;       // f_delay_group
            mem[tmp + 7] = _0;       // phase_group
            mem[tmp + 8] = 1000_0;   // period_group  
  */   
    end
    
//  ********************* ASSIGN *******************************************************************


// ********************* ПРОЦЕССЫ ******************************************************************

    
endmodule